Full picture
Foreword
1.
Overview
▸
2.
Specifications
3.
Memory Mapping
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4.
Video Modes
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5.
Tilemap Memory
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6.
Tileset Memory
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7.
Sprites Memory
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8.
Font Memory
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9.
Palette Memory
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10.
System Configuration
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11.
Video Configuration
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12.
Text Controller
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13.
SPI Controller
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14.
CRC32 Controller
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15.
Sound Controller
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16.
DMA Controller
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17.
Timer Controller
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1

Overview

1.1 Components

The Zeal Video Board is a compact 5×10 cm (1.97×3.94 in) daughterboard, built entirely with SMD components.

Its main connection point is the Bus Connector (17). This single port can power the board and allow the CPU to communicate with it. Naturally, you’ll also need to connect the VGA port to see any video output.

If you plan to use DMA, you must also connect the DMA Port — these two pins correspond to the Z80’s BUS_REQ and BUS_ACK signals.

The image below labels all major components and connectors on the board:

Zeal Video Board
  1. Lattice ECP5 FPGA (25k LUTs)
  2. 5x8-bit bidirectional shift registers (5V <-> 3.3V)
  3. SPI NOR Flash (containing the firmware and recovery mode)
  4. 50MHz oscillator
  5. Voltage regulator (5V -> 3.3V/2.5V/1.1V)
  6. Quad operational amplifier (op-amp)
  7. Volume wheel
  8. 3.5mm jack sound output
  9. Recovery mode switch
  10. LED indicators (currently used for recovery mode and reset signal)
  11. TF card slot, check the SPI controller for more details
  12. 16-bit Digital-Analog converter
  13. VGA port
  14. Power LED
  15. USB Type-C power input (only for debugging or flash the board without connecting to the video port)
  16. DMA port (BUS_REQ and BUS_ACK signals), check the DMA controller for more details
  17. Bus Connector
  18. 2x8 pin extension port
  19. JTAG port (unpopulated)

1.2 Bus Connector Pinout

The bus connector is as follows (front view of it):

Zeal Video Board Bus Connector
Pin Direction Description
A21-A17 Bidirectional Upper bits of the physical address of the 8-bit computer. On boot and reset, the FPGA maps its VRAM at 0x100000 (1MB). In other words, it will select itself if A21, A19, A18 and A17 are LOW and A20 is HIGH. As such, on computers that don't have such a big physical address space can consider these pins as chip selects.
A16-A0 Bidirectional Lower bits of the physical address of the 8-bit computer. Since the FPGA uses 128KB of memory, 17 bits are required. Check the memory mapping below for more information.
D7-D0 Bidirectional Data bus, input when the board is selected and WR is asserted (low), output when the board is selected and RD is asserted (low)
$\overline{\text{RESET}}$ Bidirectional Reset signal, active-low. This signal must be in an open-drain configuraiton. Even though this signal is bidirectional, the video board currently never asserts it itself.
$\overline{\text{RD}}$ Bidirectional Read signal, active-low. This signal is used to notify the board that a READ is requested by the motherboard. This is used in both IOREQ and MREQ. Even though this signal is bidirectional in hardware, the video board currently only uses it as input.
$\overline{\text{WR}}$ Bidirectional Write signal, active-low. This signal is used to notify the board that a WRITE is requested by the motherboard. This is used in both IOREQ and MREQ. Even though this signal is bidirectional in hardware, the video board currently only uses it as input.
$\overline{\text{MREQ}}$ Bidirectional Memory request signal, active-low. This signal is used to notify the board that a MEMORY REQUEST is requested by the motherboard. This follows the Z80 bus segmentation with a memory bus that makes us the use of all the address lines, and an I/O bus that only makes the use of the lowest 8 address lines (8-bit). Even though this signal is bidirectional in hardware, the video board currently only uses it as input.
$\overline{\text{IOREQ}}$ Bidirectional I/O request signal, active-low. This signal is used to notify the board that an I/O REQUEST is requested by the motherboard. During this request, only the lower 8-bit of address will be taken into account. For 8-bit computers that don't have such bus and only have a memory bus, this signal can be hardwired to HIGH. All the I/O modules can also be accessed via the memory bus. Check the memory mapping below for more information. Even though this signal is bidirectional in hardware, the video board currently only uses it as input.
$\overline{\text{INT1}}$ Output (3.3V) General purpose interrupt signal, active-low. This output signal notifies the motherboard when a peripheral has a pending interrupt. It is currently not used but it is planned to have SPI, sound, timer and graphics interrupts. This line must NEVER be wired to a voltage higher than 3.3V to prevent damaging the FPGA!
$\overline{\text{INT0}}$ Output (3.3V) V-blank interrupt signal, active-low. This output signal notifies the motherboard that the display component just entered v-blank state. This line must NEVER be wired to a voltage higher than 3.3V to prevent damaging the FPGA!