Zeal Video Board presents a a few registers that can be used to connfigure the currently mapped I/O controller as well the physical video memory.
These configuration area's base address on the I/O bus is 0x90, it is never mapped out, so it is available at any time.
10.2 Firmware Version
The Zeal Video Board runs thanks to an FPGA, its firmware is located on an SPI NOR Flash. This gives the possibility to the user to update the firmware at any time, using a JTAG connector or even a CPU connected to the main port, thanks to the SPI controller. Check the Recovery mode chapter for more information.
Firmware versions follow the conventional vx.y.z semantic versioning format, where x indicates the major version, y the minor version, and z the revision number.
The first three registers in the system configuration area represent the current firmware version: revision, the minor and the major, in that order.
As of today, two firmware versions have ever been released, the first beta one, v0.1.0, and the first release v1.0.0.
10.3 Scratch registers
This configuration area includes four general-purpose scratch registers, SCRATCH0, SCRATCH1, SCRATCH2, and SCRATCH3, that can be used freely by the host. Because this area is always mapped, it can simplify context switches or transitions between user and kernel modes by eliminating the need to modify main memory or the current stack.
10.4 I/O Controllers
To reduce the number of registers to allocated on the I/O bus for the Zeal Video Board, the I/O controller (such as SPI, DMA, etc...) are banked. The register MAPPED_DEVICE can be used to read the current mapped controller or write a new controller to map. The available controllers are:
As said previously, the Zeal Video Board embeds its own video RAM, so it doesn't need to us the host's RAM. Despite its size of around 80KB, it needs an address space of 128KB, because of the alignment constraint of the sub-systems (such as 64KB tileset memory).
Zeal Video Board expects the physical address space of the computer it will be connected to be 4MB big, hence the 22 address bits present on the main connector. Moreover, it doens't present any explicit chip enable line, the goal being to reduce the required external logic. Indeed, the the upper 5 bits of the 22 address lines will be compared against the PHYS_ADDR register.
As such, by configuring the register, we can configure the physical addresses ZVB will respond to.
For example, the default value of this register upon reset is 8, this means that ZVB will be mapped from physical address 8 << (22 - 5) = 8 << 17 = 0x100000 up to 0x11ffff (128KB).
Any-width address bus
Most computers, particularly 8-bit systems, do not expose a full 22-bit address bus. To allow compatibility with a wide range of hosts, the upper 5 address lines, A21 down to A17, are interpreted as chip enable signals.
These signals are internally compared against the PHYS_ADDR register. By default, this register is set to 8 after reset. Therefore, we can interpret these chip enable signals as:
A21: active low
A20: active high
A19: active low
A18: active low
A17: active low
Example: 8-bit computer with banked memory
Consider an 8-bit system, based on the Z80 CPU, with a 64KB address space organized as follows:
0x0000-0x7FFF: Internal ROM
0x8000-0xFFFF: Banked memory
It also includes an I/O port at address 0x42, which controls an 8-bit bank register, allowing up to 256 memory banks.
Since the banked memory space is 32KB big, we need to allocate 128KB / 32KB = 4 banks to ZVB. Let's assign banks 0 to 3 to ZVB, the rest of the banks can be allocated to RAM or any other component.
To interface ZVB with this computer, we would have something like this:
Interfacing with an 8-bit computer
When the Z80 CPU accesses the ROM, 0x0000-0x7FFF, the adress line A15 will be 0, so ZVB won't be selected and won't react. When banked memory is accessed, ZVB will react only if the the bank's pin 7, 6, 5, 4, 3 and 2 are low. In other words, it will be selected only if the current bank value is 0, 1, 2 or 3.
