Timer Controller

17.1 Overview

The Timer Controller provides a simple yet flexible 16-bit timer clocked by the main 50Hz system clock. It can count up or down toward zero, supporting one-shot or auto-reload modes to measure time intervals or generate periodic events.

A programmable 16-bit clock divider slows down the base clock to suit slower components or desired timing intervals. The timer can be started, stopped, reset, and configured through its registers.

Like other controllers, the DMA Controller can be mapped into the device bank, starting at address 0xA0 on the I/O port. Its device index is 6.

17.2 Operation

The Timer counts toward zero, either by incrementing or decrementing a 16-bit accumulator depending on the configured direction:

• When the timer is enabled (ENABLE bit set in CTRL register), the accumulator updates once every clock cycle defined by the clock divider (see below).
• If counting up (DIR = 0 in CTRL register), the accumulator increases by 1 each tick until it wraps and reaches zero.
• If counting down (DIR = 1in CTRL register), the accumulator decreases by 1 each tick until it reaches zero.
• When the accumulator hits zero:
  • If AUTO_RELOAD is enabled, the accumulator is immediately reset to the reload value and counting continues, creating a periodic timer.
  • If AUTO_RELOAD is disabled, the timer stops by clearing the ENABLE bit, effectively performing a one-shot timer.

You can reset the timer at any time by writing to the RESET bit, which immediately loads the reload value into the accumulator.

Reading and writing the current counter value is done through the two registers CNT_LO and CNT_HI, providing a consistent 16-bit snapshot by latching the low byte first.

This flexible behavior allows the Timer Controller to be used for precise timing, event generation, or periodic interrupts (when polled or extended with interrupt support later).

⚠️ All 16-bit values (clock divider, reload, and counter) must be written with the least significant byte (LSB) first, followed by the most significant byte (MSB). This is necessary because the controller latches the LSB on the first write and applies the full 16-bit value only after the MSB is written.

17.3 Clock Divider

The Timer Controller runs off the main 50 MHz system clock. However, many timing applications require slower intervals. To accommodate this, a 16-bit clock divider slows down the effective timer tick frequency. This clock divider can be set by writing registers DIV_LO and DIV_HI.

The divider works as a simple counter that generates a "tick" every $\text{clk_divider} + 1$ system clock cycles. This means the timer accumulator updates once every:

where:

• $T_{tick}$ is the timer tick period (seconds)
• $\text{clk_divider}$ is the 16-bit divider value programmed by the user
• $f_{clk} = 50\text{MHz}$ is the system clock frequency

For example, if clk_divider = 4999, the timer updates every:

This allows you to configure timer intervals ranging from 20 ns (fastest, with divider = 0) up to about 1.31 ms (max divider = 65535) per timer tick.

17.4 Registers Summary

17.5 Registers